1. Field of the Invention
This invention relates to computer systems, and more particularly, to an apparatus and a method for testing to determine that a system has a sufficient voltage level to write to static random access memory (SRAM) during the entire period of the write operation.
2. History of the Prior Art
There are situations in which it is desirable to transfer data stored in a non-volatile memory such as an EPROM to volatile memory. For example, when a computer system is initially turned on, the basic input/output startup (BIOS) program typically stored in non-volatile memory in Intel based computers may be transferred to main memory so that its operations become available more rapidly to the central processing unit.
In some arrangements in which data stored in a non-volatile memory is transferred to volatile memory, the volatile memory is a static random access memory (SRAM) array. It is necessary before such a SRAM array is loaded to make sure that sufficient voltage levels are available to assure that data may be written accurately to the SRAM cells. This same requirement may occur when writing to other memory devices, as well. This is a particular problem when a computer is first being turned on because the operating conditions have often not yet stabilized and great demands are being placed on its power supply. To assure that sufficient voltage is available to write to the SRAM cells of the SRAM array, a voltage detector circuit is typically utilized. This voltage detector allows the SRAM cells to be written only after the power supply voltage Vcc has reached an appropriate level. Once the detector is satisfied, writing may take place at any time. In many circuits, such a voltage level detector is all that is required. However, in computers and similar systems which operate at lower levels of power or which for other reasons are able to furnish only limited voltages, the margin for error in the power supply voltage may be sufficiently small that variations in the voltage actually available, the temperature of the circuit, and other characteristics often reduce the voltage level below that level which was initially available, often to a point at which the SRAM cells are in fact not able to be accurately written.
It is therefore desirable to provide circuitry for accurately testing the amount of power supply voltage available during the entire period in which a volatile memory array is being written from a non-volatile storage in order to assure that the data is written accurately.